1. Field of the Invention
This invention relates to the fabrication of self-aligned complementary bipolar and complementary metal oxide semiconductor (CBiCMOS) transistors on the same substrate in a common fabrication method, and more particularly to CBiCMOS fabrication techniques in which some of the process steps are used simultaneously for both the bipolar and MOS fabrication, thereby reducing the total number of steps. The invention also relates to a compatible precision resistor fabrication technique.
2. Description of the Related Art
Several BiCMOS fabrication processes have been developed to provide bipolar and CMOS devices on the same wafer. Examples of such processes are described in Charles M. Hochstedler, "The BiCMOS Edge: Fast Speed and Low Power", Semiconductor International, April 1989, pages 68-71; Alvarez et al., "Tweaking BiCMOS Circuits By Optimizing Device Design", semiconductor international, May 1989, pages 226-232; Haken et al., "Solving the Process Integration Challenges of BiCMOS", Semiconductor international, May 1989, pages 240-245; Haken et al., "BiCMOS Processes for Digital and Analog Devices", Semiconductor International, June 1989, pages 96-100; Cosentino et al., "Motorola's BiCMOS Process", Semiconductor International, June 1989, page 102; Richards et al., "Fujitsu's BiCMOS Process", Semiconductor International, June 1989, page 104; Lee et al., "Bi-CMOS Technology for High-Performance VLSI Circuits", VLSI Design, August 1984, pages 98-100; Kubo et al., "Perspective on BiCMOS VLSI's", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, Feb. 1988, pages 5-11; Chiu et al., "Non-overlapping Super Self-Aligned BiCMOS with 87 ps Low Power ECL", IEDM, 1988, pages 752-755; Chapman et al., "Submicron BiCMOS Well Design For Optimum Circuit Performance", IEDM, 1988, pages 756-759; Kobayashi et al., "High Performance LSI Process Technology: SST CBI-CMOS", IEDM, 1988, pages 760-763; Zimmer et al., "BiCMOS: technology and circuit design", Microelectronics Journal, Vol. 20, Nos. 1-2, 1989 Elsevier Science Publishers Ltd., England, pages 59-75; Deferm et al., "Latch-up In a BiCMOS Technology", IEDM, 1988, pages 130-133; Verdonckt-Vandebroek et al., "High Gain Lateral Bipolar Transistor", IEDM, 1988, pages 406-409; Goodman et al., "Complementary BMOS/BiCMOS Technology For Power IC Application", IEDM, 1988, pages 796-799; Sakui et al., "A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistor", IEDM, 1988, pages 44-45; Yuzuriha et al., Submicron Bipolar-CMOS Technology Using 16 GHzf.sub.r Double Poly-Si Bipolar Devices", IEDM, 1988, pages 748-751; Brassington et al., "An Advanced Single-Level Polysilicon Submicrometer BiCMOS Technology", IEEE Transactions on Electron Devices, Vol. 36, No. 4, Apr. 1989, pages 712-719; Kobayashi et al., "Bipolar CMOS-merged Technology for a High-Speed 1-Mbit DRAM", IEEE Transactions on Electron Devices, Vol. 36, No. 4, Apr. 1989, pages 706-711; Doyle et al., "Circuit Modeling of Bipolar Transistor for BiCMOS", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, Feb. 1989, pages 189-193; Rosseel et al., "Influence of Device Parameters on the Switching Speed of BiCMOS Buffers", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, Feb. 1989, pages 90-99; and Kertis et al , "A 12-ns ECL I/0256K.times.1-bit SRAM Using a 1-.mu.m BiCMOS Technology", IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, Oct. 1988, pages 1048-1053. These types of circuits are useful in applications such as high performance and high precision analog/digital mixed signal processing.
As with circuit processing in general, in CBiCMOS fabrication it is always desirable to reduce the number of fabrication steps required. For example, separate series of process steps have previously been required to form the CMOS gates and the bipolar emitter and base regions. The bipolar base and emitter regions have themselves been formed separately, which not only adds to the process steps required but also can result in a degradation of the emitter-base breakdown voltage. Excessive substrate-to-collector capacitance has also been a problem, limiting the bipolar transistor's speed of response and consequently the attainable bandwidth.
Another problem has been a tendency to form a sharp discontinuity in the dopant concentration at the edge of the emitter region, which leads to abrupt changes in the electric field in this area and a consequent lowering of the emitter-base breakdown voltage. It would be preferable to have a more gradual dopant gradient at the edge of the emitter region, with an accompanying smoothing out of the electric field gradient.
NiCr resistors have also been employed in the fabrication of CBiCMOS circuitry. While providing good resistance characteristics, this material produces a high contact resistance to metallization contacts that can increase the effective overall resistance beyond design values. It would therefore be highly desirable to retain the advantageous resistance properties of NiCr, but to reduce the level of associated contact resistance.